This invention relates, in general, to CMOS delay lines.
CMOS delay lines are often used for high frequency clock synchronization for video signals and parallel micro controller units (MCU).
A CMOS delay line is generally composed of multiple CMOS inverters or a cascaded CMOS inverter chain such as 32-stage series inverters. Each inverter, or cascaded inverter, has a slightly different rise and fall time as well as slightly different threshold voltage. Such variations are caused by small geometric mismatches of the transistors and stray capacitance around the transistors.
As a digital signal is propagated through the multiple or cascaded inverters, the small variations in rise and fall times accumulate. The output duty cycle time of the signal (duty cycle time is the portion of the input signal registering a high, or above the threshold voltage) will be changed from the original input signal to be delayed.
A worst case scenario involves a high frequency input signal having a low duty cycle time. In this case, the output pulse can become very narrow and generate a clock re-synchronization malfunction in the circuits the delay line is outputting to.
To avoid the problems of signal mismatching and narrow output pulses, the duty cycle time must be controlled to maintain a duty cycle approximately equal to the input signal duty cycle.
Furthermore, it is desirable to maintain a certain duty cycle range generated by each individual delay inverter. This allows control of the total duty cycle generated by the entire string or series of delay inverters.